Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability.

Microchip's nationally-recognized Leadership Passage Programs support growth opportunities where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip.

Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. An opening exists for Tech Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products.

This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip’s Best-In-Class engineering practices. Own design planning and construction of pad rings, bump patterns, ensuring alignment with package and system-level constraints.

Develop, implement, and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the design cycle.



Generate and validate physical design handoff deliverables including pad ring DEF files, Verilog netlists, bump maps, and associated implementation data for downstream teams. Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.

Collaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to align on IO/package requirements and resolve technical issues.

Support

Verification, Emulation, ASIC validation, and silicon debug efforts by analyzing IO-related issues and driving design improvements. S. degree in electrical engineering with 12+ years related experience. Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.

Experience with IO planning and implementation EDA tools (e.g., Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off). Understanding of Foundation and Hard IP related views including RTL, lef and liberty. Working proficiency in flow automation and scripting using tcl and/or python.

S. degree in electrical engineering. Basic understanding of DFT methodologies mainly JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation for including post-silicon bring-up and debug flows for SoC IO validation. Working knowledge of Industry standard Project management, versioning and tracking tools e.g.

Travel Time: 0% - 25% It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health perks that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. As one of the top performing semiconductor companies in the world, we are led by a set of guiding values and a mission to empower innovation to enhance the human experience.

📌 Technical Implementation Engineer (Burnaby)
🏢 FHLB Des Moines
📍 Burnaby