Elevate your career as an ASIC Verification Expert for a distinguished client developing state-of-the-art ASICs. Utilize your extensive experience in System Verilog, UVM, and verification methodologies to contribute in a dynamic team.
As an ASIC Verification Engineer, you will be at the forefront of creating and executing rigorous verification plans. Your role is pivotal in leading the development of a robust verification infrastructure and implementing effective test strategies to ensure the highest quality of digital ASICs.
Key Responsibilities:
• Develop and lead verification infrastructure for advanced designs
• Create System Verilog/UVM protocol generators and checkers
• Execute and develop comprehensive test plans based on standards
• Define and run self-checking tests for complex ASICs
Requirements:
• Bachelor’s in computer science or electrical engineering
• 8+ years of ASIC verification experience
• Proven track record in developing test plans
• Proficient in System Verilog and Python scripting
• Robust UVM methodology knowledge
Leverage your ASIC verification skills to shape cutting-edge designs in this critical role.
#J-18808-Ljbffr