Join Synopsys as a Senior ASIC Design Engineer and work remotely or hybrid while specializing in digital logic and high-speed SerDes technology. Your decade of experience will drive significant design impacts.
This role at Synopsys demands expertise in ASIC design and mentorship of junior engineers. You will critically analyze and translate complex interface specifications while collaborating across teams. With a focus on design intent and verification, your contributions will directly improve the quality and performance of industry-leading silicon solutions.
Key Responsibilities:
• Design digital subsystems for Ethernet and PCIe technologies
• Analyze digital and analog interface specifications
• Drive design flow decisions and low-power strategies
• Work with verification teams on assertion reviews
• Mentor junior engineers on RTL quality
Requirements:
• Master's degree in relevant engineering field
• 10+ years of hands-on digital design experience
• Solid skills in RTL design with Verilog/VHDL
• Understanding of timing closure and power optimization
• Experience with high-speed digital interfaces
Lead design innovation in high-volume products at Synopsys while making a real-world impact.
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