Join HCLTech as a Design Lead, focusing on ASIC/SoC projects. Leverage your expertise in testbench development with 5-7 years of experience to make a difference.

In this senior role at HCLTech, you will define TB architectures and develop comprehensive test plans for ASIC/SoC verification. Your technical skills will be critical in building and maintaining reusable testbenches using SystemVerilog and UVM. Engage in rigorous debugging and ensure high standards of quality through functional coverage analysis.

Key Responsibilities: • Participate in full chip ASIC/SoC verification • Develop reusable block-level and sub-system testbenches • Code and execute functional coverage and assertions • Debug complex simulation issues with EDA tools • Analyze coverage metrics and ensure test quality

Requirements: • 5 to 7 years of hands-on ASIC/SoC experience • Robust command of Verilog, SystemVerilog, and UVM • Knowledgeable in digital logic design and clocking concepts • Skilled with EDA tools like QuestaSim and Xcelium • Basic experience in scripting languages for automation

Contribute your expertise in ASIC/SoC verification and design at HCLTech. #J-18808-Ljbffr

📌 Design Lead for ASIC/SoC at HCLTech (East Gwillimbury)
🏢 HCL Technologies
📍 East Gwillimbury