Join Synopsys as a Senior ASIC Design Engineer and work remotely or hybrid while specializing in digital logic and high-speed SerDes technology. Your decade of experience will drive significant design impacts.This role at Synopsys demands expertise in ASIC design and mentorship of junior engineers. You will critically analyze and translate complex interface specifications while collaborating across teams. With a focus on design intent and verification, your contributions will directly improve the quality and performance of industry-leading silicon solutions.Key Responsibilities:Design digital subsystems for Ethernet and PCIe technologiesAnalyze digital and analog interface specificationsDrive design flow decisions and low-power strategiesWork with verification teams on assertion reviewsMentor junior engineers on RTL qualityRequirements:Master's degree in relevant engineering field10+ years of hands-on digital design experienceStrong skills in RTL design with Verilog/VHDLUnderstanding of timing closure and power optimizationExperience with high-speed digital interfacesLead design innovation in high-volume products at Synopsys while making a real-world impact.#J-18808-Ljbffr