Join Microchip Technology as a Principal RTL Design Engineer to shape the technology that powers our world. This role is focused on cutting-edge RTL design and verification for advanced mixed-signal IP.As part of the Mixed Signal Development Group, you will work on the entire ASIC design cycle, collaborating with various engineering teams. Your focus on designing RTL using advanced languages like Verilog/SystemVerilog will be crucial as you tackle the challenges of integrating and verifying subsystem blocks. This position requires strong problem-solving skills and a proactive approach to design challenges.Key Responsibilities:Lead the ASIC design process,



including verification and debuggingDesign RTL and integrate IP blocks using Verilog/SystemVerilogRun simulations and perform power analysisCollaborate with teams for timing closure and DFT tasksDevelop test plans and support silicon bring-upRequirements:Advanced degree in Electrical or Computer Engineering2-10 years of experience in ASIC developmentStrong skills in RTL design and verification toolsHands-on experience in debugging with EquipmentFamiliarity with C/C++, Python, or similar scripting languagesBring your engineering skills to Microchip, where innovation meets opportunity.#J-18808-Ljbffr

📌 Mixed Signal Rtl Engineer Position (Burnaby)
🏢 Microchip Technology
📍 Burnaby