Join a leading client as a Senior ASIC Verification Engineer focused on complex digital ASICs. Your expertise in System Verilog, UVM, and test plan execution is essential in this team-oriented environment.This role requires extensive experience to develop and verify advanced ASIC designs. You'll lead the verification infrastructure, create protocol generators, and define self-checking tests. Your contributions will ensure rigor in functional requirements and adherence to industry standards, all within a geographically diverse team.Key Responsibilities:Lead development of verification infrastructure for ASIC designsCreate protocol and traffic generators in System Verilog/UVMDevelop and execute comprehensive test plansDefine and run self-checking tests for digital ASICsRequirements:Bachelor's in computer science or electrical engineeringOver 8 years in ASIC verificationProven experience in test plans at block/sub-chip levelsProficiency in System Verilog and PythonDeep knowledge of UVM methodologyBring your ASIC verification expertise to an impactful role that drives technical excellence.#J-18808-Ljbffr

📌 Senior Asic Verification Engineer Role (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 Myticas Consulting
📍 Riviere-des-Prairies—Pointe-aux-Trembles