Join us in Ottawa as a Memory Layout Engineer, specializing in advanced-node technology. This role focuses on memory layout development and integration into SoC designs.

As a Memory Layout Engineer, you will leverage your expertise to optimize layouts for control circuits, bit-cell arrays, and decoders. You will handle physical verification, focusing on DRC, LVS, and density checks, while ensuring compliance with IR drop and electromigration standards. Collaborating with circuit, physical design, and process teams is essential in achieving design goals.

Key Responsibilities: • Optimize sense amplifier and I/O block layouts • Integrate memory solutions within SoC hardware • Conduct thorough physical verification and signoff processes • Execute DRC, LVS, and density check procedures • Resolve IR drop and electromigration challenges

Requirements: • Extensive experience with TSMC 4nm to 7nm nodes • Comprehensive understanding of memory architecture design • Bachelor’s/Master’s in Electrical or Electronics Engineering • Excellent debugging and problem-solving capabilities • Must be local to Ottawa for onsite work

Bring your memory layout expertise to this energetic role in Ottawa. #J-18808-Ljbffr

📌 Ottawa Memory Layout Engineer Role (Montreal)
🏢 Value Innovation Labs
📍 Montreal