Join Microchip Technology as a Principal RTL Design Engineer to shape the technology that powers our world. This role is focused on innovative RTL design and verification for advanced mixed-signal IP.

As part of the Mixed Signal Development Group, you will work on the entire ASIC design cycle, collaborating with various engineering teams. Your focus on designing RTL using advanced languages like Verilog/SystemVerilog will be crucial as you tackle the challenges of integrating and verifying subsystem blocks. This position requires solid problem-solving skills and a proactive approach to design challenges.

Key Responsibilities: • Lead the ASIC design process,



including verification and debugging • Design RTL and integrate IP blocks using Verilog/SystemVerilog • Run simulations and perform power analysis • Collaborate with teams for timing closure and DFT tasks • Develop test plans and support silicon bring-up

Requirements: • Advanced degree in Electrical or Computer Engineering • 2-10 years of experience in ASIC development • Strong skills in RTL design and verification tools • Hands-on experience in debugging with Equipment • Familiarity with C/C++, Python, or similar scripting languages

Bring your engineering skills to Microchip, where innovation meets opportunity. #J-18808-Ljbffr

📌 Mixed Signal RTL Engineer Position (Burnaby)
🏢 Microchip Technology
📍 Burnaby