We are looking for a highly skilled Memory Layout Engineer with robust expertise in advanced node technologies to support high-performance semiconductor designs. The ideal candidate will have hands‐on experience in memory layout development, physical verification, and top-level integration across SRAM and other memory architectures on TSMC FinFET processesKey ResponsibilitiesDesign and implement custom layouts for memory blocks, including:Develop and optimize layouts for critical memory components such as:Perform top-level memory integration, ensuring seamless assembly of memory macros within SoC environmentsExecute and resolve physical verification checks, including:Density checksDrive layout cleanup and signoff closure, ensuring high-quality tapeout readinessAnalyze and mitigate IR drop and EM (Electromigration) issues in memory layoutsCollaborate with circuit design, physical design,



and process teams to ensure optimal performance, area, and powerRequired QualificationsBachelor's/master's degree in electrical/Electronic Engineering or related fieldProven experience in memory layout design at advanced technology nodesHands‐on experience with TSMC 7nm FinFET technologyPreferred QualificationsExperience with TSMC 6nm / 5nm / 4nm / 3nm technologiesStrong understanding of memory architecture and layout methodologiesFamiliarity with industry-standard layout and verification tools (e.G., Virtuoso, Calibre)Key SkillsPhysical verification (DRC, LVS, Density)IR/EM analysis and mitigationTop-level memory integrationStrong problem‐solving and debugging skills #J-18808-Ljbffr

📌 Memory Layout Engineer (Boucherville)
🏢 Conjoint
📍 Boucherville