Join a leading client as a Senior ASIC Verification Engineer focused on complex digital ASICs. Your expertise in System Verilog, UVM, and test plan execution is essential in this collaborative setting.

This role requires extensive experience to develop and verify advanced ASIC designs. You'll lead the verification infrastructure, create protocol generators, and define self-checking tests. Your contributions will ensure rigor in functional requirements and adherence to industry standards, all within a geographically diverse team.

Key Responsibilities:

- Lead development of verification infrastructure for ASIC designs
- Create protocol and traffic generators in System Verilog/UVM
- Develop and execute comprehensive test plans
- Define and run self-checking tests for digital ASICs

Requirements:

- Bachelor’s in computer science or electrical engineering
- Over 8 years in ASIC verification
- Proven experience in test plans at block/sub-chip levels
- Proficiency in System Verilog and Python
- Deep knowledge of UVM methodology

Bring your ASIC verification expertise to an impactful role that drives technical excellence.

📌 Senior ASIC Verification Engineer Role (Quebec)
🏢 Myticas Consulting
📍 Quebec