Commitment: Full-time preferred; high availability required (40 hours)

Duration: Target engagement of ~3+ months

Location: Remote, USA and Canada only

RTL Design Engineer
Qualifications

3-10 years of experience in digital RTL design

Strong proficiency in Verilog / SystemVerilog

Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols

Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware design

Familiarity with common EDA tools for simulation, waveform debug, lint, CDC, synthesis, timing analysis

Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows

Ability to write clear design documentation and communicate technical tradeoffs

Experience debugging RTL issues using simulation logs and waveform viewers

Strong collaboration skills across architecture, verification, and implementation teams

Preferred

AMBA protocols (AXI, AHB, APB)

Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power design





Exposure to formal verification or SV/UVM-based design verification

Design Verification Engineer
Qualifications

3-10 years of experience in design verification

Solid proficiency in SystemVerilog and UVM

Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols

Experience developing reusable verification components and testbench infrastructure

Constrained-random verification, functional coverage, assertions (SVA), coverage closure

Familiarity with EDA tools for simulation, waveform debug, coverage analysis, formal verification, regression management

Familiarity with LLM-based tools to accelerate verification, debug, test generation, documentation, or coverage analysis

Ability to write clear verification plans, debug reports, and technical documentation

Preferred

AMBA protocols (AXI, AHB, APB)

Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power verification

Reusable verification IP, scoreboards, reference models, coverage-driven regression flows

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📌 ASIC Verification Engineer - Remote (Manitoba)
🏢 YO IT CONSULTING
📍 Manitoba