Become a crucial part of a premier client's team as a Logic/Mixed-Signal Verification Engineer. This role involves ASIC verification, static timing analysis, and collaboration with various design teams.

As a Verification Engineer I, you will focus on developing verification plans and executing test strategies based on established specifications. Your primary responsibilities include leading static timing analysis efforts and executing mixed-signal verification for complex designs. Your collaboration with RTL, analog, and digital design teams is essential for achieving design quality.

Key Responsibilities:
• Develop and execute verification plans based on specifications
• Lead static timing analysis and timing closure activities




• Execute analog circuit design and comprehensive mixed-signal verification
• Debug complex issues across mixed-signal simulations
• Enhance verification flows and methodologies for efficiency

Requirements:
• BSEE, BSCE, or equivalent; MS preferred
• 1-5 years in ASIC and mixed-signal verification
• Proficient in SystemVerilog/Verilog and scripting languages
• Familiar with static timing analysis and analog design
• Solid debugging and problem-solving skills

Embrace the challenge of leading verification efforts while enhancing design quality and efficiency.
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📌 Mixed-Signal Verification Engineer Role (Ontario)
🏢 KellyOCG
📍 Ontario