Join Celero as an ASIC Design Engineer dedicated to developing optical transceivers for next-generation optical modems in Ottawa, Ontario. Leverage your HDL skills in a collaborative environment.

The successful candidate will have a vital role in designing ASICs for advanced optical technologies. With a Bachelor’s degree in Electrical or Computer Engineering and over three years of experience, you will optimize performance, perform timing analysis, and conduct RTL simulations. Your technical expertise will contribute significantly to design reviews and team guidance.

Key Responsibilities:
• Design digital circuits using HDL like Verilog/System Verilog
• Perform synthesis, timing analysis, and Clock Domain Crossing analysis
• Optimize ASIC designs for power, performance,



and area
• Execute RTL simulation and verification for functionality
• Collaborate on system integration and validation

Requirements:
• Bachelor’s degree in relevant engineering field
• 3+ years of digital design experience
• Proficiency in HDL and knowledge of ASIC tools
• Familiarity with verification methodologies
• Robust problem-solving and communication skills

Become a key player in the future of optical technology with Celero by applying your digital design expertise.
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📌 ASIC Design Engineer for Optical Modems (Quebec City)
🏢 CELERO COMMUNICATIONS
📍 Quebec City