Join Synopsys as a Senior ASIC Digital Architect with hybrid or remote flexibility from anywhere in Canada. Bring a decade of high-speed digital design and mentorship experience to our creative team.
This role involves architecting and designing digital subsystems for various high-speed standards including Ethernet and PCIe. You will troubleshoot and refine designs while ensuring high-quality output through direct collaboration with ASIC verification engineers. Mentoring junior engineers is critical to spreading knowledge and establishing best practices within the team.
Key Responsibilities:
• Design digital subsystems for high-speed interfaces
• Analyze specifications and derive implementable RTL
• Make informed decisions regarding low-power architecture
• Work with verification teams to improve test coverage
• Conduct timing analysis and debug failures
Requirements:
• Master’s degree in Electrical Engineering or equivalent
• 10+ years in digital ASIC design
• Expertise in Verilog or VHDL for RTL design
• Solid understanding of synthesis and DFT practices
• Experience with Ethernet, PCIe, SATA, or USB PHYs
Your impactful design work will define the next generation of connectivity solutions at Synopsys.
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