Join us as a SERDES PHY Mixed Signal Design Engineer! Work on pre-silicon and post-silicon phases to ensure high-quality performance in CLIENT SoC environments.
This position emphasizes electrical analyses to guarantee successful operation of SERDES PHY IP. A background in mixed signal design, particularly related to SERDES or memory PHY, is key. Experience in functional validation and a solid grasp of clock specifications will enhance your contributions.
Key Responsibilities:
• Support integration and testing of SERDES PHY IP
• Analyze power, signal, and clock integrity issues
• Work closely with post-silicon teams on compliance testing
• Participate in production screening and characterization
• Leverage lab experience for functional testing
Requirements:
• Design experience focusing on SERDES or memory PHY
• Knowledge of power noise and signal integrity concepts
• Understanding of termination impedance and transmission lines
• Basic mastery of clock specifications like jitter
• Experience with functional validation in a lab setting
Utilize your technical skills in mixed signal design for critical applications within our team.
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