Drive cutting-edge PCI Express developments at AMD as a Senior ASIC Design Engineer. Leverage your expertise in RTL design to enhance silicon performance and quality in a collaborative, innovative setting.In this critical role, you will contribute to IP RTL design for AMD's PCIe IP used across various next-gen products, including servers and GPUs. Your responsibilities include micro-architecting innovative features, applying low power design techniques, and ensuring high-quality RTL through timing and closure verification.



Your dedication to meeting development goals will be crucial as you work independently and within a team to solve complex technical challenges.Key Responsibilities:Design RTL for AMD's PCI Express IPCollaborate with architects on cutting-edge featuresApply low power techniques for improved system performanceEnsure quality through timing and LINT closureSupport ASIC verification and debugging stagesRequirements:Bachelor's or Master's in Computer/Electrical EngineeringStrong Verilog HDL RTL coding experienceFamiliarity with AI-assisted design methodologiesExperience with multiple clock domainsKnowledge of high-speed I/O protocolsUtilize your RTL expertise and collaborative spirit at AMD to shape the future of computing.#J-18808-Ljbffr

📌 Senior Asic Design Engineer At Amd (Markham)
🏢 AMD
📍 Markham