Our client is a leader in next-generation digital connectivity, enabling high-performance data communication across the most demanding industries—ranging from AI and the metaverse to data centers, 5G infrastructure, and autonomous vehicles. They deliver mission-critical IP through innovative engineering and a proven execution track record. As a Staff Physical Design Engineer , you’ll take ownership of implementing, optimizing, and verifying complex digital designs at the physical level.

You’ll work alongside front-end designers, DFT engineers, and verification teams to ensure the delivery of high-quality silicon. This role focuses on advanced-node physical implementation—floor planning, PnR, CTS, timing closure, and sign-off verification. Drive all stages of physical design including floor planning, placement, CTS, routing, and optimization for high-speed digital blocks.

Own timing closure strategies, including skew balancing, delay optimization, and ECO implementation. Perform signal/power integrity analysis including IR drop and electromigration. Collaborate across design, DFT, verification, and process teams to resolve implementation or manufacturability issues.

Build and maintain automation scripts (TCL, Python, Perl) to streamline flows and improve efficiency. 5+ years of experience in physical design for digital ASICs. Deep understanding of PnR, CTS, STA, IR/EM analysis, and power optimization techniques. Familiarity with DFT techniques such as scan insertion, ATPG, or BIST is a plus.

Strong scripting capabilities in TCL, Python, or Perl. Analytical mindset with a data‑driven approach to debugging and problem‑solving.

Staff Physical Design Engineer





Our client is a leader in next-generation digital connectivity, enabling high-performance data communication across the most demanding industries—ranging from AI and the metaverse to data centers, 5G infrastructure, and autonomous vehicles. They deliver mission-critical IP through cutting-edge engineering and a proven execution track record. As a Staff Physical Design Engineer , you’ll take ownership of implementing, optimizing, and verifying complex digital designs at the physical level.

You’ll work alongside front-end designers, DFT engineers, and verification teams to ensure the delivery of high‑quality silicon. This role focuses on advanced-node physical implementation—floor planning, PnR, CTS, timing closure, and sign‑off verification. Drive all stages of physical design including floor planning, placement, CTS, routing, and optimization for high‑speed digital blocks.

Own timing closure strategies, including skew balancing, delay optimization, and ECO implementation. Perform signal/power integrity analysis including IR drop and electromigration. Collaborate across design, DFT, verification, and process teams to resolve implementation or manufacturability issues.

Build and maintain automation scripts (TCL, Python, Perl) to streamline flows and improve efficiency. 5+ years of experience in physical design for digital ASICs. ~ Deep understanding of PnR, CTS, STA, IR/EM analysis, and power‑optimization techniques. ~ Familiarity with DFT techniques such as scan insertion, ATPG, or BIST is a plus. ~ Strong scripting capabilities in TCL, Python, or Perl. ~ Analytical mindset with a data‑driven approach to debugging and problem‑solving.

📌 Technology Design Engineer (Toronto)
🏢 Talentlab
📍 Toronto