with solid expertise in advanced-node technologies and hands-on experience in memory layout development, physical verification, and top-level integration.
Layout optimization for Sense Amplifiers, Control Circuits, I/O Blocks, Bit-Cell Arrays & Decoders
Top-level memory integration within SoC environments
Physical verification and signoff closure
DRC, LVS & Density Checks
IR Drop and Electromigration ( EM ) analysis and mitigation
Collaborate with Circuit Design, Physical Design & Process teams
Hands-on experience with
TSMC 7nm FinFET
Physical Verification – DRC, LVS, Density
Solid debugging and problem-solving skills
Experience with
TSMC 6nm / 5nm / 4nm / 3nm
Solid understanding of memory architecture and layout methodologies
Education:
Bachelor’s/Master’s in Electrical/Electronics Engineering or related field.
Onsite Requirement:
Candidates must be able to commute to the Ottawa, Ontario location.
J-18808-Ljbffr
📌 Memory Layout Engineer Montreal (Canada)
🏢 Value Innovation Labs
📍 Canada
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.