We are looking for a highly skilled Memory Layout Engineer with robust expertise in advanced-node technologies and hands-on experience in memory layout development, physical verification, and top-level integration.
Layout optimization for Sense Amplifiers, Control Circuits, I/O Blocks, Bit-Cell Arrays & Decoders
Top-level memory integration within SoC environments
Physical verification and signoff closure
DRC, LVS & Density Checks
IR Drop and Electromigration (EM ) analysis and mitigation
Collaborate with Circuit Design, Physical Design & Process teams
Hands-on experience with TSMC 7nm FinFET
Physical Verification – DRC, LVS, Density
Robust debugging and problem-solving skills
Experience with TSMC 6nm / 5nm / 4nm / 3nm
Robust understanding of memory architecture and layout methodologies
Education: Bachelor’s/Master’s in Electrical/Electronics Engineering or related field.
Onsite Requirement: Candidates must be able to commute to the Ottawa, Ontario location.
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