- Responsible for RTL design using Verilog HDL for implementation and debug.
- Read and comprehend System on Chip level architectural specification.
- Write microarchitecture specifications for recent and modified functions.
- Responsible for linting and simulation of design.
- Work with synthesis and backend teams for physical implementation.
- RTL Design Engineer to help with some IP work
- Need experience with some AI tools, how to use AI tools to speed up the development
- Basic infrastructure knowledge
EDUCATION:
- Bachelor's or Master's in Computer Engineering.
📌 Senior Design Engineer (Toronto)
🏢 Net2Source (N2S)
📍 Toronto
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