At AMD, our mission is to build excellent products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Join us as we shape the future of AI and beyond. The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team.

We develop leading‑edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. You will be involved in all aspects of IP design starting from architecture to requirements to execution. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market.

The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The ideal candidate is a detail‑oriented and driven ASIC design engineer who enjoys solving complex technical challenges and seeing work through to successful completion. You are proactive, adaptable, and comfortable navigating ambiguity while maintaining a focus on quality and execution.

Success in this role requires sound technical judgment, effective time management, and the ability to clearly communicate technical concepts, status, and risks to diverse audiences. In this role, you will work closely with IP and SoC design teams across the globe to drive design quality, support integration, and help resolve complex synthesis, timing, and physical implementation challenges. You will have the opportunity to contribute to high‑impact technology, collaborate with multi‑disciplinary engineering teams,



and help advance AMD's ability to deliver industry‑leading products to market.

Understand the functional and performance requirements of the IOHUB within various SOCs Drive IP/SOC design infra decisions to ensure consumption within the context of the SOC Provide guidance and/or act as a liaison between IP and SOC design teams for synthesis and physical layout issues Scope requirements and resources to meet project schedules Provide hands‑on leadership of a small team of Engineers/Engineers in Training as required to meet program development goals Sign‑off IP quality for delivery into SOC Gather, attend and present into technical status meetings on a weekly/bi‑weekly basis Proven ASIC design experience, RTL design experience on large ASIC development projects Formality, CDC & Linting tools, Design Compiler/FX etc) Academic Experience Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.

AMD’s “Responsible AI Policy” is available here.

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