Drive cutting-edge PCI Express developments at AMD as a Senior ASIC Design Engineer. Leverage your expertise in RTL design to enhance silicon performance and quality in a collaborative, innovative setting.

In this critical role, you will contribute to IP RTL design for AMD’s PCIe IP used across various next-gen products, including servers and GPUs. Your responsibilities include micro-architecting innovative features, applying low power design techniques, and ensuring high-quality RTL through timing and closure verification. Your dedication to meeting development goals will be crucial as you work independently and within a team to solve complex technical challenges.

Key Responsibilities:
• Design RTL for AMD’s PCI Express IP
• Collaborate with architects on cutting-edge features




• Apply low power techniques for improved system performance
• Ensure quality through timing and LINT closure
• Support ASIC verification and debugging stages

Requirements:
• Bachelor’s or Master’s in Computer/Electrical Engineering
• Solid Verilog HDL RTL coding experience
• Familiarity with AI-assisted design methodologies
• Experience with multiple clock domains
• Knowledge of high-speed I/O protocols

Utilize your RTL expertise and collaborative spirit at AMD to shape the future of computing.
#J-18808-Ljbffr

📌 Senior ASIC Design Engineer at AMD (Ontario)
🏢 AMD
📍 Ontario