Engineering Group, Engineering Group ASICS Engineering As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. You will lead and drive physical design implementation for complex, large-scale retimer-class and full-reticle ASIC products in advanced technology nodes. This role requires strong technical leadership to synthesize ambiguous requirements, drive execution across cross-functional teams, and deliver high-quality silicon meeting aggressive power, performance, and area (PPA) targets.

Replacement Position

Lead and execute end-to-end Physical Design flow for SoC and retimer ASICs, including: Clock Tree Synthesis (CTS) Power Delivery Network (PDN) Timing analysis and closure Design-for-manufacturability (DFM) Design-for-yield (DFY) Collaborate with cross-functional engineering teams (front-end, analog/SerDes, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions Develop and improve physical design methodologies and flows to enhance efficiency and scalability Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR Bachelor’s degree and 4+ years of progressive experience in ASIC Physical Design or related domain End-to-end ASIC Physical Design flow Solid understanding of: Experience with full-reticle or near-reticle SoC implementation Exposure to data center, networking,



or optical connectivity ASICs Strong scripting and automation skills (Python, Tcl) Effective collaboration across global, cross-functional engineering teams Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. We also offer a competitive annual discretionary bonus program and chance for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. #

📌 Staff Engineer, Physical Design/Implementation (Toronto)
🏢 Socket.dev
📍 Toronto