Synopsys, Inc. is seeking an experienced digital ASIC design lead in Canada to architect SerDes IP for Backplane Ethernet, PCIe, SATA, and USB PHYs. You will work across RTL, synthesis, and verification, shaping clock domain crossing and power-aware design decisions. You will mentor engineers, collaborate with verification and implementation teams, and guide testplans and coverage strategies. The role offers a path to impact silicon products shipped worldwide, with a team of experts tackling #J-18808-Ljbffr