Elevate your engineering career as a Memory Layout Engineer in Ottawa, Ontario. This role requires expertise in advanced-node technologies, memory layout development, and physical verification.

We seek a skilled Memory Layout Engineer with a strong background in optimized layout for memory architecture. Your responsibilities will include top-level memory integration in SoC environments and ensuring design rule check (DRC), layout versus schematic (LVS), and density checks. You will also address IR drop and electromigration analysis while collaborating with circuit, physical design, and process teams.

Key Responsibilities:



• Optimize layouts for Sense Amplifiers and I/O Blocks • Ensure top-level memory integration within SoC environments • Conduct physical verification and signoff closure • Perform DRC, LVS, and density checks • Analyze IR drop and electromigration issues

Requirements: • Proven experience with TSMC 3nm to 7nm technologies • Robust understanding of memory architecture and layout methodologies • Bachelor’s/Master’s in Electrical/Electronics Engineering • Robust debugging and problem-solving skills • Ability to commute to Ottawa location

Contribute your expertise in memory layout and physical verification to advance cutting-edge technology in Ottawa. #J-18808-Ljbffr

📌 Memory Layout Engineer Ottawa, Ontario (Montreal)
🏢 Value Innovation Labs
📍 Montreal