Astera Labs is looking for a Physical Design Engineer specializing in timing closure for our advanced ASIC designs. This role is fully in office and vital for our AI infrastructure initiatives. In this critical position, you will focus on timing analysis and sign-off throughout the design process.

Collaborate closely with RTL, physical design, and verification teams to support the development of complex ASICs for leading service providers. Your technical proficiency will drive the integrity of our custom connectivity solutions in cloud-based applications. Key Responsibilities:
Manage timing closure from RTL to sign-off for complex SoCs
Validate SDC constraints and facilitate productive STA analysis
Apply leading sign-off methodologies at advanced technology nodes




Generate timing ECOs with collaboration across teams
Offer actionable feedback for timing convergence and improvements Requirements:
Bachelor’s in Electrical Engineering or Computer Science required
Minimum 5 years of timing analysis experience with SoCs
Expertise in STA methodologies and timing constraints
Solid understanding of synthesis and place-and-route flows
Proficiency with physical design tools and scripting languages Use your expertise to drive innovation in AI solutions with Astera Labs.

📌 Physical Design Engineer For Timing Closure Solutions Toronto
🏢 Astera Labs
📍 Toronto