13 Aug
|
Talentlab
|
Winnipeg
13 Aug
Talentlab
Winnipeg
Talentlab partners with a leading global semiconductor company to recruit a Staff ASIC Design Engineer for AI/ML hardware IP. The role emphasizes RTL design, micro-architecture development, and hardware integration with a focus on clock domain crossing, power optimization, and formal verification.
The candidate should have extensive hands-on ASIC experience including Verilog/SystemVerilog, CDC/Lint tools, and various synthesis/timing environments.
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📌 Senior ASIC Design Engineer — AI/ML Hardware IP Architect (Winnipeg)
🏢 Talentlab
📍 Winnipeg