Expert Physical Design Engineer At Qualcomm (Toronto)

Expert Physical Design Engineer At Qualcomm (Toronto)

13 Aug
|
Astera Labs
|
Toronto

13 Aug

Astera Labs

Toronto

Drives planning, coordination, and execution for connectivity ASIC design, focusing on timing closure from RTL to sign-off. Requires expertise in STA, SDC constraints, and advanced node methodologies.

📌 Expert Physical Design Engineer At Qualcomm (Toronto)
🏢 Astera Labs
📍 Toronto

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