Become an ASIC Verification Engineer at Synopsys, specializing in high-performance HBM projects. Utilize your experience with SystemVerilog and advanced methodologies to enhance verification quality. We invite a highly experienced engineer committed to excellence in ASIC verification.

With at least 10 years of experience, you will develop rigorous verification plans and actively engage in debugging and analysis with multi-disciplinary teams. This role promotes collaboration and continuous learning in a agile setting. Key Responsibilities:
Create and execute verification plans for complex designs
Maintain and write advanced test cases in SystemVerilog/UVM
Collaborate closely with design teams to resolve issues
Automate testing workflows for enhanced coverage and productivity
Document methodologies and outcomes for knowledge sharing Requirements:
Bachelor’s or Master’s degree in Electrical Engineering
10+ years in digital verification experience
Expertise in writing test cases using SystemVerilog/UVM
Solid debugging skills for complex issues
Proficient in scripting languages for automation Drive innovation and excellence in ASIC verification with your expertise at Synopsys.

📌 Asic Verification Engineer For Hbm Products Ottawa (Canada)
🏢 Synopsys
📍 Canada