12 Aug
|
Talentlab
|
Canada
Talentlab partners with a leading global semiconductor company to recruit a Staff ASIC Design Engineer for AI/ML hardware IP. The role emphasizes RTL design, micro-architecture development, and hardware integration with a focus on clock domain crossing, power optimization, and formal verification.
The candidate should have extensive hands-on ASIC experience including Verilog/SystemVerilog, CDC/Lint tools, and various synthesis/timing settings.
J-18808-Ljbffr
📌 Senior Asic Design Engineer — Ai/ml Hardware Ip Architect Toronto (Canada)
🏢 Talentlab
📍 Canada