Qualcomm Canada ULCJob Area Engineering Group GPU ASICS EngineeringGeneral Summary Architects, designs, implements, verifies, and optimizes performance and power of GPU cores. Responsible for verification of Graphics IP, and performing pre- and post-silicon verification to verify correctness and ensure performance and power goals are met. Applying independent creative thought to troubleshoot technical problems or deal with novel circumstances. some limited data analysis may be required.

Applies graphics knowledge and experience to architect, design, implement, and verify the structure and performance of GPU hardware, drivers, features, applications, and tools. Creates and maintains verification test benches and environments in System Verilog/UVM. Creates and leverages advanced testing frameworks to generate and recreate real‑world system integration conditions.

Collaborates with Architecture, Software, Firmware, Design, Modeling, Emulation and Post‑silicon validation teams to define and develop test methodology and content. Collects, organizes and executes various forms of system level test content including directed testcases, gaming benchmarks, standards compliance test suites, and system level scenarios. Builds automation for continuous integration and testing based on latest GPU IP.

Helps collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues. Writes technical documentation and feature descriptions for straightforward projects under the direction of a supervisor. Bachelor's degree in Computer Engineering,



Computer Science, Electrical Engineering, or related field plus 4+ years of related work experience.

Master's degree in same fields plus 3+ years of related work experience. PhD in same fields plus 2+ years of related work experience. 5+ years Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. ~ Test planning, Scripting, Simulation, problem solving, and debugging. ~ System Verilog, UVM, Verilog or VHDL, C/C++ skills required. ~ Constrained random, functional coverage development, design debug experience required. ~ Master's Degree in Electrical or Computer Engineering, Computer Science, or related field. ~Concurrency, preemption, stress testing frameworks. Testbench architecture and implementation.

Scripting and automation skills (Python, Make, Airflow, etc.). Benchmarking and performance analysis. Windows and/or Linux OS kernel architecture. C/C++, GNU Toolchain, Visual Studio. Embedded firmware and/or kernel level development and debugging skills (C/C++, Makefile, gdb, uboot, uefi, kernel‑mode drivers). additional annual discretionary bonus program and RSU grants may be offered.

Employees are eligible for a competitive advantages package supporting work, home, and personal life. If you are an individual with a disability and need an accommodation during the application/hiring process, please e‑mail disability‑[email protected] will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process.

📌 Validation Systems Design Engineer (Markham)
🏢 Qualcomm
📍 Markham