Tech Lead - Memory Layout Engineer (FinFET, 3nm/5nm) (Vancouver)

Tech Lead - Memory Layout Engineer (FinFET, 3nm/5nm) (Vancouver)

11 Aug
|
K&K Global Talent Solutions
|
Vancouver

11 Aug

K&K Global Talent Solutions

Vancouver

K&K; Global Talent Solutions INC. is seeking an experienced Technology Lead – Memory Layout Engineer to design and develop high-performance memory layouts for advanced semiconductor technologies.

The role requires expertise in memory layout, physical verification, and FinFET architectures, with hands-on Cadence Virtuoso and Calibre experience. The candidate will optimize layouts for performance, power, and area, and collaborate with cross-functional teams to ensure timely project delivery.

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📌 Tech Lead - Memory Layout Engineer (FinFET, 3nm/5nm) (Vancouver)
🏢 K&K Global Talent Solutions
📍 Vancouver

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