Take your engineering expertise to the next level as a Staff Engineer for Layout Design at Synopsys, specializing in analog layouts and automating verification processes.

In this role, you will focus on creating optimized analog mixed-signal layouts while ensuring high standards of device matching and parasitic performance. The position demands 5+ years of relevant experience, and proficiency with tools like Custom Compiler SDL or Virtuoso XL.

By performing detailed verification checks, you will reduce rework and enhance team productivity through automation and effective documentation.

Key Responsibilities:
Create and optimize layouts with a focus on matching performance
Oversee top-down floor planning coordination
Execute DRC, LVS,



and Antenna verifications with precision
Lead PERC verification to mitigate design risks
Share best practices across global layout teams

Requirements:
Bachelor's or Master's degree in Electrical Engineering or Computer Science
5+ years of analog layout experience required
Proficient in Custom Compiler SDL or Virtuoso XL
Extensive knowledge of verification processes
Scripting skills in TCL, Perl, or Python are advantageous

Drive innovation in layout design and contribute to impactful projects at Synopsys!
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📌 Staff Engineer For Layout Design At Synopsys Markham (Canada)
🏢 Synopsys
📍 Canada