10 Aug
Talentlab
Toronto
Talentlab is seeking a seasoned ASIC verification engineer in Ontario with 9+ years of experience. You will architect and verify DSPs, build UVM testbenches, and own verification lifecycle from plans to sign-off for tape-out.
The role is hybrid in the GTA or Ottawa, requiring SystemVerilog, UVM, and familiarity with PCIe/Ethernet, SerDes. You will mentor juniors and collaborate with the design team to deliver robust digital designs.
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.