Join Synopsys as a Senior Staff ASIC Engineer specializing in Physical Design, where your innovation will shape next-generation chip technologies. Leverage your vast experience in SoC implementations and physical design flows.In this role, you will engage in the comprehensive development process of test chips, ensuring high-quality IP solutions that meet demanding performance standards. With over nine years in the field, your responsibilities will encompass optimizing the RTL-to-GDSII design flow and managing cross-functional collaborations to drive project success. You will champion continuous improvement, enhancing both design automation and efficiency.Key Responsibilities:
Lead physical design for test chips using cutting-edge technologies
Optimize design paths for area, power, and performance
Conduct timing analysis and verification for high-accuracy results
Support the release of updated design documentation
Coordinate closely with architecture and verification teamsRequirements:
Minimum 9 years of experience in ASIC design
Extensive knowledge of ASIC flow from synthesis to signoff
Proficiency in tools such as RedHawk and PrimeTime
Experience in project leadership and execution
Must have valid authorization to work in the USAYour role will directly contribute to Synopsys’s reputation as a leader in high-performance silicon solutions.#J-18808-Ljbffr