Our client is seeking a highly experienced ASIC Verification Engineer to help develop and verify complex digital ASICs in a collaborative, geographically diverse workplace.Key ResponsibilitiesLead the development of verification infrastructure for advanced ASIC designsCreate System Verilog/UVM-based protocol and traffic generators/checkersDevelop and execute test plans based on functional and standards requirementsDefine, develop, and run self-checking tests for complex digital ASICsRequired QualificationsBachelor’s degree in computer science or electrical engineering (master’s preferred)8+ years of experience in ASIC verificationProven experience in developing and implementing test plans at block or sub-chip levelsProficiency in System Verilog and scripting languages such as PythonDeep understanding of UVM methodologyExperience with assertions, functional coverage, code coverage, and formal verification toolsStrong communication skills and ability to work effectively in a distributed teamPreferred SkillsKnowledge of DSP and/or FEC technologies#J-18808-Ljbffr