Seeking an ASIC Design Verification Engineer to develop and debug models, create verification plans, build test benches, and contribute to AI/ML-enhanced verification flows. Requires proficiency in SystemVerilog, Python, Perl, C-Shell, and Cadence SKILL, plus UVM experience.
📌 Asic Design Verification Engineer - $124,200 - $174,200 A Year (Markham)
🏢 Qualcomm Canada ULC
📍 Markham
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