Astera Labs is looking for a Physical Design Engineer specializing in timing closure for our advanced ASIC designs. This role is fully on-site and vital for our AI infrastructure initiatives. In this critical position, you will focus on timing analysis and sign-off throughout the design process.
Collaborate closely with RTL, physical design, and verification teams to support the development of complex ASICs for leading service providers. Your technical proficiency will drive the integrity of our custom connectivity solutions in cloud-based applications. Validate SDC constraints and facilitate effective STA analysis
- Bachelor’s in Electrical Engineering or Computer Science required
- Minimum 5 years of timing analysis experience with SoCs
- Proficiency with physical design tools and scripting languages Use your expertise to drive innovation in AI solutions with Astera Labs.
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📌 Design Engineer, Labs (Toronto)
🏢 Astera Labs
📍 Toronto
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