Join the leading chiplet startup! As an Eliyan Staff Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs. You will own verification of TX/RX equalization and CDR. This is a hands-on technical leadership role. You'll define PHY verification architecture, write UVM/SV testbenches, and make sure that designs are bug free. You will work with a cross-functional team of experts. We offer a fun work setting with excellent benefits. ONSITE M-F.Key ResponsibilitiesDevelop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR.Create and maintain SystemVerilog/UVM-based verification environmentsWrite and debug SystemVerilog/UVM compliant test cases for block and chip levelMaintain regression environmentsCollaborate with design team to ensure design qualityDevelop, maintain,



and track various test plan items and progress towards RTL freezeStay up to date with industry trends, emerging technologies and progress in standards' bodiesIntegration of 3rd party VIPs and coordinate feature/bug tracking requestsAs a technical leader, mentor junior verification engineersGLS simulation for functional verification and power calculationsRequired QualificationsBS + 7 years of verification experience with 4+ years in PHY or high-speed interfacesDeep verification expertise in SerDes/PCIePHY, TX/RX equalization, CDRStrong expertise in UVM/SystemVerilog, test environment and assertion codingExperience in verifying mixed signal IPs as well as integration of VIPsPreferred Qualifications10+ years with demonstrated verification technical leadershipExperience with Formal verification with Jasper Gold or vc-formalExperience with GLS simulationsPython/Perl/Tcl scripting for design verificationProficiency in 3rd party tools for regression management and coverage analysis #J-18808-Ljbffr

📌 Dv - Staff Verification Engineer - Serdes (Toronto)
🏢 Eliyan
📍 Toronto