Company: Qualcomm Canada ULCJob Area: Engineering Group, Engineering Group > ASICS EngineeringGeneral SummaryThe successful candidate will join the Display IP Design team in developing leading edge display solutions in Qualcomm SoC's. We are looking for individuals that possess internal drive and keen desire to learn on the job. You will work within a multi-disciplinary, multi-site team of architects, designers and verification engineers and will be responsible for the IP design development and integration within the display sub-system. New PositionPrincipal DutiesDevelop Micro-Architecture and specification based on high level design requirementsDevelop RTL design that meets required performance and is optimized for area and powerIntegrate pre-verified sub-IPs to build up larger functionalityFlow bring up and report analysis for linting, RTL synthesis, CLP, CDCWork closely with verification team to define test plan, debug regression, analyze coverage reportsDevelop SVA assertions for white box verification for formal verificationEffective communication across teams, multitasking and well-planned execution of the tasksPreferred QualificationsPrior experience delivering Verilog and System Verilog RTLDetail oriented with strong analytical and debugging skillsStrong communication (written and verbal), collaboration, and specification skillsPracticed design knowledge working with some of the following conceptsClock domain crossing and reset architectureMachine Learning HW developmentFIFOs implementationBus implementation/verification techniquesMemory selection and controlHigh speed and low power design optimizationBus interface protocols (AHB, AXI)Experience with some of the followingSimulation and code coverage tools (VCS, Verdi, Modeltech/Questa,



or Xcelium)Design rule and CDC checking (SVA assertions, Spyglass, 0-in, etc.)Scripting languages (PERL, Python, TCL, C, etc.)Power Intent and Analysis: UPF, CLP, PTPX, PowerProSynthesis: DCG/NXT, FCStatic Timing: PrimetimeFormal Verification: Conformal, FormalityMinimum QualificationsLegally permitted to work in office in Canada2+ years of ASIC design experienceEffective educational background: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experienceor Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experienceor PhD in Science, Engineering, or related fieldEqual Opportunity and Accommodation StatementQualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm's toll-free number to request reasonable accommodations.Pay range and Other Compensation & BenefitsPay: $104,900.00 - $154,900.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.Contact InformationFor more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

📌 Senior Asic Display Design Engineer (Markham)
🏢 Qualcomm
📍 Markham