Shape the future of memory technology at Synopsys as a Senior Staff Engineer in ASIC Digital Design. This role focuses heavily on RTL design for High Bandwidth Memory PHY IP with a blend of digital and mixed-signal expertise. In this senior role, you will leverage your 7-10 years of hands-on experience to drive cutting-edge RTL implementations using SystemVerilog and Verilog.

You will collaborate with diverse teams to address high-speed design and integration challenges, contributing to the development of industry-leading memory bandwidth solutions. Your profound knowledge of ASIC design will enable you to mentor junior engineers while pushing technical boundaries in cutting-edge projects. Key Responsibilities:

- Deliver RTL designs for High Bandwidth Memory PHY IP
- Translate architectural requirements into robust RTL implementations




- Collaborate with cross-functional design teams for optimal performance
- Innovate solutions for timing closure and low power design
- Automate design tasks using scripting languages to improve efficiency Requirements:
- 7-10 years of RTL design experience
- Expertise in SystemVerilog and Verilog
- Strong background in high-speed and low power design
- Familiarity with DFT/DFM and complex hardware debugging
- Proficiency in scripting languages like Python or Perl Bring your high-speed design expertise and leadership skills to Synopsys, shaping the next generation of computing technology.

📌 Senior Staff Engineer, ASIC Digital Design (Canada)
🏢 Synopsys
📍 Canada