09 Aug
|
Talentlab
|
Ontario
Talentlab is seeking a Senior Design Verification Engineer to join its Digital Design Verification team. You will review design specs, develop robust verification plans, build testbenches, run simulations, and debug issues to uncover design bugs across data‑heavy domains including SerDes, DSPs, and mixed‑signal blocks.
The role requires 3–8 years of verification experience with SystemVerilog/UVM, plus familiarity with Ethernet and PCIe protocols, formal verification, and UPF techniques.
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📌 Lead Digital Design Verification Engineer (Ontario)
🏢 Talentlab
📍 Ontario