Risc-V Design Verification Engineer (Mid-Staff) - $80,000 - $250,000 A Year (Richmond)

Risc-V Design Verification Engineer (Mid-Staff) - $80,000 - $250,000 A Year (Richmond)

08 Aug
|
Andes Technology
|
Richmond

08 Aug

Andes Technology

Richmond

Design Verification Engineer role at Andes Technology, verifying RISC-V CPUs, requiring experience with Verilog, System Verilog, and CPU architecture.

📌 Risc-V Design Verification Engineer (Mid-Staff) - $80,000 - $250,000 A Year (Richmond)
🏢 Andes Technology
📍 Richmond

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