Elevate your career as an Expert ASIC Design Architect with Synopsys and lead the charge in silicon innovation. Your extensive background in mixed-signal verification and automation will drive excellence in high-performance chip solutions.
This role requires over a decade of expertise in ASIC development and a hands-on approach to mixed-signal verification. You will implement critical test plans and build verification environments using UVM and SystemVerilog. Collaboration with stakeholders is essential for ensuring project milestones are met and best practices are disseminated throughout the team.
Key Responsibilities:
• Implement Unified Test Plans for DSP-based PHY products
• Establish robust UVM verification environments
• Develop and share scripts for automation based on multiple programming languages
• Engage with stakeholders to tackle technical issues
• Design and execute test plans for high-speed data recovery
Requirements:
• 10+ years in ASIC development and mixed-signal experience
• Proficient in PCIe, Ethernet protocols, and digital processing
• Deep knowledge of SystemVerilog and UVM
• Robust scripting skills including Perl, Python, C++
• Proven record of delivering within tight deadlines
Lead cutting-edge developments in ASIC design and contribute to Synopsys' legacy of technological advancement.
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