Take the lead as a Senior SerDes Architect at Synopsys, working on advanced optical communication systems that drive the future of data technology. Leverage your expertise in analog design and modeling.
This architect role offers a unique chance to shape high-speed SerDes IP solutions vital for PCIe Gen6+ and 200G+ Ethernet. At Synopsys, you'll address complex challenges related to system performance and design feasibility while collaborating with experts in various domains. Your ability to correlate models with actual silicon results will be key in delivering reliable solutions.
Key Responsibilities:
• Construct MATLAB and Simulink models for SerDes systems
• Perform sign-off simulations to ensure target specifications
• Develop algorithms for real-time performance adjustments
• Link simulation results closely with silicon measurements
• Collaborate with clients and internal teams for optimal solutions
Requirements:
• M.Sc. or Ph.D. in relevant technical fields
• Established expertise in SerDes modeling and high-speed communications
• Experience with analog CMOS design and equalization methods
• Familiarity with systems integration and optical testing
• Proven ability to debug and update models based on results
Drive innovation and excellence at Synopsys, where your contributions matter.
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