We are looking for a highly skilled Memory Layout Engineer with strong expertise in advanced node technologies to support high-performance semiconductor designs. The ideal candidate will have hands-on experience in memory layout development, physical verification, and top-level integration across SRAM and other memory architectures.
Responsibilities
Design and implement custom layouts for memory blocks, including:
SRAM
Register Files
ROM
TCAM
Develop and optimize layouts for critical memory components such as:
Sense amplifiers
Control circuits
I/O blocks
Bit-cell arrays
Decoders
Perform top-level memory integration, ensuring seamless assembly of memory macros
within SoC environments
Execute and resolve physical verification checks, including:
DRC (Design Rule Check)
LVS (Layout vs Schematic)
Density checks
Drive layout cleanup and signoff closure, ensuring high-quality tapeout readiness
Analyze and mitigate IR drop and EM (Electromigration) issues in memory layouts
Collaborate with circuit design, physical design,
and process teams to ensure optimal
performance, area, and power
Required Qualifications
Bachelor’s/Master’s degree in Electrical/Electronics Engineering or related field
Proven experience in memory layout design at advanced technology nodes
Hands-on experience with 7nm FinFET technology
Preferred Qualifications
Experience with 6nm / 5nm / 4nm / 3nm technologies
Robust understanding of memory architecture and layout methodologies
Familiarity with industry-standard layout and verification tools (e.g., Virtuoso, Calibre)