Elevate your career as a Lead ASIC Digital Design Engineer with Synopsys, specializing in creative High Bandwidth Memory designs. Drive advancements in digital and mixed-signal technology in a collaborative environment.As part of our High Bandwidth Memory PHY RTL team, you will apply 7-10 years of ASIC design expertise to tackle complex challenges. Your knowledge of RTL development and physical implementation will be instrumental in product development. Mentor junior engineers and support the integration of high-quality IP into customer SoCs.Key Responsibilities:Lead RTL design for cutting-edge HBM PHY IPConvert high-level architecture into functional RTLCollaborate with teams in analog and physical designInnovate timing closure strategies and low power techniquesAutomate verification processes to streamline workflowsRequirements:7-10 years of RTL design experienceStrong familiarity with SystemVerilog and VerilogExpertise in timing closure and high-speed designComprehensive knowledge of ASIC development phasesProficiency with automation using scripting toolsJoin Synopsys and leverage your digital design skills to contribute to pioneering memory interface solutions.#J-18808-Ljbffr

📌 Lead Asic Digital Design Engineer At Synopsys (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 Synopsys
📍 Riviere-des-Prairies—Pointe-aux-Trembles