Role OverviewDesign and implement custom layouts for memory blocks, including:Develop and optimize layouts for critical memory components such as:Perform top-level memory integration, ensuring seamless assembly of memory macros within SoC environmentsExecute and resolve physical verification checks, including:Density checksDrive layout cleanup and signoff closure, ensuring high-quality tapeout readinessAnalyze and mitigate IR drop and EM (Electromigration) issues in memory layoutsCollaborate with circuit design, physical design, and process teams to ensure optimal performance, area,



and powerRequired QualificationsBachelor's/Master's degree in Electrical/Electronics Engineering or related fieldProven experience in memory layout design at advanced technology nodesHands-on experience with TSMC 7nm FinFET technologyPreferred QualificationsExperience with TSMC 6nm / 5nm / 4nm / 3nm technologiesStrong understanding of memory architecture and layout methodologiesFamiliarity with industry-standard layout and verification tools (e.G., Virtuoso, Calibre)Key SkillsPhysical verification (DRC, LVS, Density)IR/EM analysis and mitigationTop-level memory integrationStrong problem-solving and debugging skillsThis role is considered an in office position located in Ottawa, Ontario, CANADAYou must be able to commute to and from the location with your own transportation arrangements to meet the required working hours #J-18808-Ljbffr

📌 Memory Layout Engineer (Riviere-des-Prairies—Pointe-aux-Trembles)
🏢 SRA Group
📍 Riviere-des-Prairies—Pointe-aux-Trembles