Harness innovation at Microchip Technology as a Principal RTL Design Engineer. This pivotal role involves designing high-performance analog and mixed-signal circuits, requiring expertise in RTL design and verification.In the Mixed Signal Development Group, your contributions will enhance various divisions. You'll collaborate with talented engineers throughout the ASIC development lifecycle and utilize advanced CMOS processes. Proficiency in Verilog/SystemVerilog is necessary, alongside a passion for developing cutting-edge integrated circuits for wireline applications.Key Responsibilities:Oversee complete ASIC design from verification to debuggingImplement RTL designs using Verilog/SystemVerilog and integrate blocksPerform simulations, lint checks,



and run CDC analysisWork with cross-functional teams on timing closure and debuggingCreate high-quality documentation for design and testingRequirements:Bachelor's/Master's/PhD in Electrical/Computer Engineering2-10 years of relevant ASIC development experienceExperience in RTL design and verification requiredFamiliarity with lab debugging equipmentKnowledge of C/C++ and scripting languages advantageousLeverage your RTL design expertise to contribute to transformative projects at Microchip.#J-18808-Ljbffr

📌 Principal Engineer Rtl Design Role (Burnaby)
🏢 Microchip Technology
📍 Burnaby